Detailed Description of the
Preferred Embodiments

Continuation...

  To improve response speed in shared processing involving a significant number of slave PC's 1, a virtual potential parallel processing network for PC's 1 in a cluster 101 preferably is established before a processing request begins.  This is accomplished by the transponder device 120 in each idle PC 1, a potential slave, broadcasting by transponder 120 its available state when it becomes idle and/or periodically afterwards, so that each potential master PC 1 in the local cluster 101 is able to maintain relatively constantly its own directory 121 of the idle PC's 1 closest to it that are available to function as slaves.  The directory 121 contains, for example, a list of about the standard use number of slave PC's 1 for the master PC (which initially probably is just one other PC 1") or a higher number, preferably listed sequentially from the closest available PC to the farthest. The directory of available slave PC's 1 is preferably updated on a relatively up to date basis, either when a change occurs in the idle state of a potential slave PC in the directory 121 or periodically.

 Such ad hoc clusters 101 should be more effective by being less arbitrary geographically, since each individual PC is effectively in the center of its own ad hoc cluster. Scaling up or down the number of microprocessors required by each PC at any given time is also more seamless.

 The complete interconnection potentially provided optimally by such ad hoc wireless clusters is also remarkable because such clusters mimics the neural network structure of the animal brain, wherein each nerve cell, called a neuron, interconnects in a very complicated way with the neurons around it.  By way of comparison, the global network computer described above that is expected in a decade can have at least about 10 times as many PC 's as a human brain has neurons and they can be connected by electromagnetic waves traveling at close to the speed of light, which is about 300,000 times faster than the transmission speed of human neurons (which, however, are much closer together).

 An added note: as individual PC's continue becoming much more sophisticated and more network oriented, compatibility issues may decrease in importance, since all major types of PC's will be able to emulate each other and most software, particularly relative to parallel processing, may no longer be hardware specific.  However, to achieve maximum speed and efficiency, it is beneficial to set compatible hardware, software, firmware, and other component standards to realize potential performance advantages attainable with homogeneous parallel processing components of the global network computer.

 Until that compatibility or homogeneity is designed into the essential components of network system, the existing incompatibility or heterogeneity of current components increase the difficulty involved in parallel processing across large networks.  Even so, the use of message passing interfaces (MPI) and parallel virtual machines (PVM), for example, has made massively parallel processing between heterogeneous personal computers fairly easy for uncoupled operations, as shown for example in the Beowulf operating system, Globus, and the Legion system, from which has been derived Applied Meta.  Programming languages like Java is one approach provides a partial means for dealing with the heterogeneity problem, whereas Linux provides greater speed and efficiency.  In addition, using similar configurations of existing standards, like using PC's available on the Internet (with its vast resources) with a specific Intel Pentium chip with other identical or nearly identical PC components is probably the best way in the current technology to eliminate many of the serious existing problems that can easily be designed around using available technologies by adopting reasonable consensus standards for homogeneous specification of all parallel processing system components, both networks and computers.  The potential gains to all parties with an interest far outweigh the potential costs.

 The above described global network computer system has an added benefit of reducing the serious and growing problem of the nearly immediate obsolescence of PC and other computer hardware, software, firmware, and other components.  Since the preferred system above is the sum of its constituent parts used in parallel processing, each specific PC component becomes less critical.  As long as access to the network utilizing sufficient bandwidth is possible, then all other technical inadequacies of the user's own PC can be completely compensated for by the network's access to a multitude of technically able PC's of which the user will have temporary use.

 Although the global network computer will clearly cross the geographical boundaries of nations, its operation is not likely to be unduly bounded by inconsistent or arbitrary laws within those individual states. There will be considerable pressure on all nations to conform to reasonable system architecture and operational standards generally agreed upon, since the penalty of potential exclusion from a global network computer system like the Internet/WWW is potentially so high as to not be politically possible any in any country.

 As shown in Figure 15, because the largest number of user PC's are completely idle, or nearly so, during the night, it can be useful for the most complicated large scale parallel processing, involving the largest numbers of processors with uninterrupted availability as close together as possible, to be routed by the network to geographic areas of the globe undergoing night and to keep them there even as the Earth rotates by shifting computing resources as the world turns.  As shown in the simplest case in Figure 15, during the day, at least one parallel processing request by at least one PC 1 in a network 2 in the Earth's western hemisphere 131 are transmitted by very broad bandwidth connection wired 99 means such as fiber optic cable to the Earth's eastern hemisphere 132 for execution by at least one PC 1' of a network 2', which is idle during the night and the results are transmitted back by the same means to network 2 and the requesting at least one PC 1.

 Any number of individual PC's within local networks like that operated by an ISP can be grouped into clusters or cells, as is typical in the practice of the network industry.  As is common in operating electrical power grids and telecommunications and computer networks, many such processing requests from many PC's and many networks could be so routed for remote processing, with the complexity of the system growing substantially over time in a natural progression.

 Alternatively, for greater security or simplicity, nighttime parallel processing can remain within a relatively local area and emphasize relatively massively parallel processing by larger entities such as business, government, or universities for relatively complicated applications that benefit from comparatively long nightly periods of largely uninterrupted use of significant numbers of slave personal computers PC 1.

 Any of the embodiments shown in Figures 1-15 can be combined with one or more of any other of Figures 1-15 of this application to provide a useful improvement over the art.

 While the conventional approach to configuring a network of personal computers PC 1 for parallel processing is simply to string them together in a simple bus-type architecture, as shown previously in Figure 9, new Figures 16A-16Z and 16AA show a new hierarchial network topology.

 Although the Figure 9 network structure is simple and produces reasonable results in loosely coupled problems like geographic searches described earlier, as a general approach it has at least three important problems.

 First, as the number of personal computers PC 1 being used in the network grows, an increasingly greater deal of complex pre-operation planning and custom tailoring-type programming at the master PC 1 level is required to establish a means for allocating portions of the operation among the large number of available personal computers PC 1'.

 Second, operations results coming back to PC 1 from personal computers PC 1' are not synchronized, so that PC 1 frequently alternates between being idle and being overwhelmed. When the number of personal computers PC 1' is very large, both problems can be significant; when the number is massive, the problems can be overwhelming and seriously degrade the operation of the network.

 Third, generally there is no means established for personal computers PC 1' to communicate or cooperate with each other during such network operations, so sharing operational results during processing between personal computers PC 1' is usually not feasible, especially when large numbers of PC 1 are involved.  Consequently, closely coupled problems are generally not amenable to solution by conventional parallel processing by computers using a simple bus-type network like Figure 9.

 The new hierarchical network topology shown in Figure 16A is a simple subdivision step whereby a personal computer PC 1 (or equivalent PC on a microprocessor chip 90) or microprocessor 30 acting as a master M₁ divides a given operation into two parts (for example, two halfs), then sends by an optical or electrical connection such as optical fiber or wire 99 the one half parts to each to two connected available slave personal computers PC 1 (or PC microprocessor 90) or microprocessor 30, as shown one processing level down as S₂₁ and S₂₂.  The Figure 16A (and subsequent Figures 16) can be connected to the Internet 3 and World Wide Web, as preferred, or may not be so connected but still with benefit.

 Figure 16B shows that slave personal computer PC 1 (or PC microprocessor 90) or microprocessor 40 located at S₂₁ has temporarily adopted the same functional role as a master to repeat the same subdivision of the given operation.  Therefore, having already been divided in half once in Figure 16A, the given operation is again subdivided in Figure 16B, this time in half into quarters of the original operation (for example) by S₂₁, which then sends one quarter to each of two additional available slave personal computers PC 1 (or PC microprocessors 90) or microprocessors 40 located at S₃₁ and S₃₂.

 Figure 16C shows personal computers PC 1 (or PC microprocessor 90) or microprocessors 40 at S₃₁ and S₃₂ sending operation results back to S₂₁ after performing the processing required by the given operation, instead of repeating again the subdivision process. That processing action by S₃₁ and S₃₂ can be dictated by pre-established program criteria, for example by automatically defaulting to operational processing at the S₃ level after two subdivision processes as shown above, so that the operation can be processed in parallel by four available slave personal computers PC 1 (or PC microprocessors 90) or microprocessors 40.  Alternately, as another example, the criteria can be a user preference command over-riding an otherwise automatic default to level three processing in order to specify some other level of processing involving more or less slave PC 1 (or PC microprocessors 90) or microprocessors 40.

 Similarly, in Figure 16A above, the personal computer PC 1 (or PC microprocessor 90) or microprocessor 40 acting as master M₁ also can initiate the parallel processing operation (or, alternatively, a multi-tasking operation) on the basis of a preset program parameters through software, hardware, or firmware or other means; parameter examples again being pre-set automatic default or user preference over-ride.

 Like Figure 16C, Figure 16D shows operation results being passed back to the next higher level, this time from slave personal computers PC 1 (or PC microprocessors 90) or microprocessors 40, S₂₁ and S₂₂, to master personal computer PC 1 (or PC microprocessor 90) or microprocessor 30, M₁, where the operation is completed after the S₂₁ and S₂₂ results are consolidated.

 Figure 16G shows master personal computer PC 1 (or PC microprocessor 90) or microprocessor 30, M₁, offloading by wireless connection 100, such as optical wireless for example, the entire parallel processing operation to an available slave personal computer PC 1 (or PC microprocessor 90) or microprocessor 40 that temporarily functions as S₁ in the place of M₁ on the first processing level for the duration of the given parallel processing (or multi-tasking) operation, the first step of which operation is shown in Figure 16H, which is like Figure 16A except as shown.

 Figure 16I shows a personal computer PC 1 (or PC microprocessor 90) or microprocessor 40 that is executing a command to function in the slave role of S₂₁ for a given operation but has become unavailable, or was unavailable initially, (due, for example, to interruption for other higher priority command by its user or to malfunction) when results of the given operation from a lower parallel processing level are passed to S_21.  In that situation, S₂₁ (or S₃₁ or S₃₂) can simply offload those results to another personal computer PC 1 (or PC microprocessor 90) or microprocessor 30 (or 40) that is then available and it can become S₂₁ and take over the role of S₂₁ in the given operation for the duration of that operation.  Similarly, the role of any unavailable or malfunctioning master or slave PC 1 or microprocessor 90, 30, or 40 can be transferred to an available functioning one.

 As shown in Figure 16J, S₂₁ then completes the parallel processing operation and passes its portion of the operation results to M₁.

 The offloading capability of functional roles of master and slave personal computers PC 1 (and PC microprocessors 90) and microprocessors 30 (and 40) from unavailable to available PC 1, 30 and 40 as shown in Figures 16G-16J can also be used in previous figures in this application.  In the simplest case initially, all processing roles of personal computers PC1 (and PC microprocessors 90) and microprocessors (30 or 40), like S₂₁, above can be determined at the beginning of an operation based on availability (based on non-use and lack of malfunctioning component) and remain unaltered until the end of the operation.  But, with more sophisticated system software and hardware and firmware, during an operation any number of the processing roles can be offloaded from personal computers PC 1 (or PC microprocessors 90) or microprocessors 30 (or 40) to others as required, even multiple times and many simultaneously.

 Figure 16E shows the multi-processing network topology of Figures 16A-16J in a larger scale embodiment, including all personal computers PC 1 (or PC microprocessors 90) or microprocessors 30 (or 40) that are participating in a typical operation, including in this example one personal computer PC 1 (or PC microprocessor 90) or microprocessor 30 (or 40) at level one; two at level two; four at level three; and eight at level four.  The network topology is completely scalar in that any practical number of additional processing levels or personal computers PC 1 (or PC microprocessors 90) or microprocessors 30 (or 40) can be added to those shown (and topologies limited to just two (or three) levels are also possible, which is the simplest case of operation processing subdivision that distinguishes over the conventional Figure 9 single level "string-together" architecture).

 Note that the number of processing personal computers PC 1 (or PC microprocessors 90) or microprocessors 40 doubles at each additional processing level and therefore can be represented by 2^N, where N is the last or final processing level, for the simplest case, as shown above, which is splitting one given operation into two parts such as halfs between each level.

 Note also that instead of subdividing one operation as above, two separate parallel processing operations can be multi-tasked on separate branches, such as S₂₁ and S₂₂ as shown, using the same network architecture described above.  As is clear from this example, any practical mix of multi-tasking and/or parallel processing is possible using the above network architecture.

 Figure 16E shows the distribution of a given parallel processing (or multi-tasking) operation as routed through a four level virtual network, beginning at M₁.  "Virtual" as used here means temporary, since in the next parallel operation originating at M₁ it might be the case that many of the personal computers PC 1 (or microprocessors 90) or microprocessors 30 (or 40) that had been available for a previous operation would not still be available for the next operation.

 As Figure 16E shows a binary tree network architecture for the initial distribution of an operation from M₁ down through four slave processing levels, while Figure 16 F shows the subsequent processing and accumulation of results back from there to M_1. Figure 16F shows an inverted view of Figure 16E to show the sequence of the operation, from operation distribution in Figure 16E to result accumulation in Figure 16F.

 More specifically, Figure 16F shows the processing slave personal computers PC 1 (or PC microprocessors 90) or microprocessors 40 at the fourth level, S₄₁ through S₄₈, where they process the operation to produce results which are then routed back through two other levels of the virtual network to M₁.

 In the routing of operation results shown in Figure 16F, each slave personal computer PC 1 (or PC microprocessor 90) or microprocessor 40) has the capability to either simply pass through those results operation only as a direct communication link or connection; or, alternatively, for example, to consolidate those results sent from the personal computers PC 1 (or PC microprocessor 90) or microprocessors 40) at a lower level; or, to provide additional other processing based on those lower processing level results.

 Such consolidation or additional processing can reduce or eliminate duplicative data from a search or other operation producing duplicative results and can also serve to buffer the originating master M₁ from overloading caused by many sets of results arriving at M₁ in the Figure 9 single processing level architecture in an uncoordinated fashion from what might be a large number of slave personal computers PC 1 (or PC microprocessor 90) or microprocessors 40.  Such a consolidation role for personal computers PC 1 (or PC microprocessor 90) microprocessors 40 substantially reduces or eliminates the excessive custom pre-planning and synchronization problems of the conventional Figure 9 network topology discussed above.

 Figure 16K shows a simple example indicative of the extremely complicated network structure that can result from subdividing a given operation in which the complexity of the operation involved is not uniform, due to, for example, variations in the data. In this example, pre-set program splitting criteria can be employed that balances the processing load of each slave personal computer PC 1 (or PC microprocessor 90) or microprocessor 40. With this approach, the complex portions of a given operation can automatically draw greater resources in the form of additional splitting of that more difficult portion of the problem, so that additional levels of parallel processing slave personal computers PC 1 (or PC microprocessors 90) or microprocessors 40 can be brought into the virtual network to process the operation, as shown in the left branch of Figure 16K.

 Figure 16K is a fairly simple example, but when the same kind of dynamic network structure is applied to a virtual network using many more personal computers PC 1 (or PC microprocessor 90) or microprocessors 30 or 40 and many processing levels, involving both micro levels in PC microprocessor chips 90 and macro levels in personal computers PC 1 networks (such as shown later in Figure 20B) then the potential complexity of the virtual network increases significantly. For example, each PC microprocessor chip 90 might have 64 slave microprocessors 94 on the final processing level; each personal computer PC 1 might have 64 slave PC microprocessor chips 90 at the final processing level, and the virtual network might include 64 personal computers PC 1 at the final processing level.  With this large number of physical resources available (which can of course be very substantially greater) to the virtual network created by processing a given operation or operations, like that shown in Figure 16K, it is clear that the operation itself can sculpt an incredibly complex virtual network that is custom tailored to the specific operation.  All that is required is a operation subdivision process as described earlier that can be resident in each PC 1 (or PC microprocessor 90) or microprocessor 30 or 40, or that can be passed along with data (as can be operation application software) as the operation is executed.

 Thus, Figure 16K shows an example of a highly flexible virtual network architecture that is capable of being dynamically configured in real time by the processing requirements imposed on the components of the network by a specific given operation and its associated data, as allowed by the network hardware/software/firmware architecture.

 Figures 16L and 16M show examples of other possible subdivision parallel processing methods, such as subdivision routing to three slave personal computers PC 1 (or PC microprocessors 90) or microprocessors 40 at the next level down, as shown in Figure 16L, or subdivision routing to four slave personal computers PC 1 (or PC microprocessors 90) or microprocessors 40, as shown in Figure 16M. Subdivision routing to any practical number of slave personal computers PC 1 (or PC microprocessors 90) or microprocessors 40 between processing levels can be done.

 Such routing subdivision can also vary between processing levels or even within the same processing level, as shown in Figure 16N; these variations examples can result from pre-set program criteria such as those that balance operation loads, like those shown previously in Figure 16K.  The means for subdividing problems for parallel or multi-tasking processing can also vary, within at least a range of methods known in the computer and mathematical arts.

 Figure 16O shows slave personal computer PC 1 (or PC microprocessor 90) or microprocessor 40, S₄₁, sending operation results to a higher processing level, S₃₁, which can then function as a router or as one or more high speed switch 42 (which can be located as 92 on a PC microprocessor 90 also, including as an all optical switch), passing through unaltered the results back down to the original level to personal computer PC 1 (or PC microprocessor 90) or microprocessor 40, S₄₂, as shown in Figure 16P.  Figure 16Q demonstrates the capability for any two pair of slave personal computers PC 1 (or PC microprocessors 90) or microprocessors 40 like S₄₁ and S₄₂ to communicate directly between each other, including wired or wirelessly 100 as shown. Figures 16O-16Q shown the same subsection of the network topology shown in Figure 16F (the left uppermost portion), as are the next Figures, 16V-16W below.

 A personal computer PC 1 (or PC microprocessor 90) or microprocessor 30 (or 40) located on a higher processing level in the network architecture such as S₃₁ can process results as well as route them, as shown in Figure 16V, in which S₃₁ receives results from S₄₁ and S₄₂ at a lower processing level and then processes that data before sending its processing results to a higher level to S₂₁, as shown in Figure 16W.

 Together, Figures 16V-16W and 16O-16Q show the capability of any personal computer PC 1 (or PC microprocessor 90) or microprocessor 30 (or 40) of the Figure 16F (and 16E) network structural and functional invention to communicate with any other personal computer PC 1 (or PC microprocessor 90) or microprocessor 30 (or 40) participating in a given parallel processing (or multi-tasking) operation.  That communication can take the form of simple pass-through of unmodified results or of modification of those results by processing at any level.

 Figures 16X-16Z show the applicant's new hierarchical network structure and function applied to the design of a personal computer PC 1, as discussed previously in Figures 10A and 10B. Figure 16X shows the simplest general design, with a master M₁ microprocessor 30 and two slave S₂₁ and S₂₂ microprocessors 40. Figure 16Y shows the same network structure with an additional level of slave microprocessors 40, S₃₁ through S₃₄, while Figure 16Z shows the same network structure as Figure 16Y with an additional level of slave microprocessors 40, S₄₁ through S₄₈.  As shown in these examples, this network structure is completely scalar, including any practical number of slave microprocessors 40 on any practical number of processing levels.

 Figure 16AA shows a useful embodiment in which each microprocessor 30 and 40 has, in addition to internal cache memory, its own random access memory (RAM) 66 or equivalent memory (volatile or non-volatile, like Flash or magnetic memory), integrated on chip or separate off chip.  A significant amount of such RAM or other memory, significantly greater than "cache" memory and other on chip memory used on microprocessor chips today, can be beneficial in improving the efficient operation of the microprocessor; if located off microprocessor chip, the size of such memory can substantially exceed the size of the associated microprocessor, but on microprocessor chip location like cache memory offers the best potential for improving microprocessor speed and efficiency.  The design can also incorporate (or substitute) conventional shared memory or RAM 66' (i.e. memory used by all, or some, of the microprocessors 30 or 40 (or 90) of the personal computer PC 1).

 Figures 16R-16T are parallel to Figures 16X-16Z above, but show PC microprocessor 90 architecture rather than macro PC 1 architecture; a PC microprocessor 90 is, of course, as earlier described in Figure 10C, a personal computer on a microchip.

 Figure 16U is like Figure 16AA, also except for showing PC microprocessor 90 architecture instead of PC 1 architecture. Figure 16U shows a useful embodiment in which each PC microprocessor 93 or 94 has its own integrated on chip (or separate off chip) random access memory (RAM) 66 or equivalent memory (volatile or non-volatile, like Flash or magnetic memory). A significant amount of such RAM or other memory, significantly greater than "cache" memory or other on chip memory used on microprocessor chips today, can be beneficial in improving the efficient operation of the microprocessor; if located off microprocessor chip, the size of such memory can substantially exceed the size of the associated microprocessor, but on microprocessor chip location like cache memory offers the best potential for improving microprocessor speed and efficiency.  The microchip design can also incorporate (or substitute) conventional shared memory or RAM 66' (i.e. memory used by all, or some, of the PC microprocessors 93 or 94 of the personal computer PC microprocessor 90).

 Figures 16R-16U show a different and improved basic chip architecture which can exclude or reduce the currently used superscalar approach in microprocessors to execute multiple instructions during each clock cycle.  The Figures 16R-16U architecture is much simpler and, by integrating memory with microprocessor, reduces memory bottlenecks.  The simplicity of the Figures 16R-16U microchip design, which might have little or no superscalar components, compared to conventional superscalar designs (the inherent extreme complexity of which creates a very substantial memory overhead) can result in the use of a much greater proportion of independent, non-superscalar processors per microchip, exclusive of integrating memory or RAM 66 onto the microprocessor chip 90, as discussed in Figure 16U.

 Figures 16X-16Z and 16AA, by using the same architecture for PC 1 networks as Figures 16R-16U, import the same advantage of microchip parallel processing performance to parallel processing in PC 1 networks.

 All Figures 16A-16Z and 16AA, like the preceding figures of this application, show sections of a network of personal computers PC 1 (or PC microprocessors 90) or microprocessors 30 or 40 which can be parts of the WWW or Internet or Internet II or the Next Generation Internet (meaning connected to it) or Intranets or Extranets or other networks.

 Also, except for Figures 16R-16T and 16X-16Z, all of the Figure 16 series show personal computers PC 1 and microprocessors 30 or 40 as occupying the same location.  This dual representation was done for economy of presentation and to show the parallel functionality and interchangability in conceptual terms of personal computer PC 1 and microprocessors 30 or 40 in the structure of the new network.  So, taking Figure 16A as an example, M₁, S₂₁ and S₂₂ show three personal computers PC 1 or, alternatively, one microprocessor 30 and two microprocessors 40.

 And, as noted initially in Figure 10C, a personal computer PC 1 can be reduced in size to a PC microprocessor chip 90, so preceding Figures showing personal computer PC 1 also generally represent PC microprocessor chip 90.

 Finally, the Figures 16A-16Z and 16AA show a mix of electrical and optical connections, including wired 99, especially connections such as optical glass fiber or omniguides, and wireless 100, especially wireless optical, (and mixtures of both in a single figure). Generally, either 99 or 100 or a mix can be used relatively interchangeably in the network inventions shown (as well as in prior figures), though in some embodiments either highest transmission speed (i.e. broadest bandwidth) or mobility (or some other factor) may dictate a preferred use of wired or wireless. Generally, fiber optic wire 99 provides the most advantageous transmission means because it has the greatest bandwidth or data transmission speed, so it is generally preferred for connections between personal computers and microchips, including direct connections, although optical wireless 100 also offers very high bandwidth; whereas other wireless 100 (but also including optical wireless), can be used where mobility is a paramount design criteria.

 The Figure 16 embodiments can be combined with, or modified by incorporating, any other network system architectures (including client/server or peer to peer) or any other topologies (including ring, bus, and star) either well known now in the art or their future equivalents or successors.

 Any of the embodiments shown in Figures 16A-16Z and 16AA can be combined with any one or more of the preceding or subsequent figures of this application to provide a useful improvement over the art.

 The parallel processing network architecture shown in the preceding Figures 16A-16Z and 16AA and in earlier figures has several features unique to its basic design that provide for the security of personal computers PC 1 (or PC microprocessor 90) or microprocessor 40 that share other computers for parallel and multi-tasking processing.  First, the slave personal computers PC 1 (or microprocessors 40) each have only part of the operation (for large operations, only a very small part) and therefore unauthorized surveillance of a single PC 1 can provide only very limited knowledge of the entire operation, especially in only a relatively local area switching or routing was employed. Second, the addresses of the slave personal computers PC 1 (or microprocessors 40) are known or traceable, therefore not protected by anonymity (like hackers usually are) in case of unauthorized intervention.  In addition, cryptography can be employed, with on microprocessor chip 30, 40, or 90 hardware 55 preferred due to efficiency, although software and firmware can also be used, or a separate PC 1 hardware-based component 56 like an encryption microchip can be used; with either encryption component 55 or 56, micro mechanical locks can be used to prevent access other than the direct physical user.  Nonetheless, these inherent strengths can be substantially reinforced, as indicated in Figures 17B-17D.

 Figure 17A shows at least one internal firewall 50 performing its conventional function of keeping out intruders such as hackers from the Internet 3 from unauthorized access for either surveillance or intervention of a user's personal computer PC 1 (or PC microprocessor 90) or master microprocessor 30.

 Figure 17B shows that, since Internet users can, as enabled by the applicant's network structure invention, use one or more of the slave microprocessors 40 of another's personal computer PC 1 (or PC microprocessor 90) for parallel (or multi-tasking) processing, the at least one internal firewall 50 has a dual function in also protecting Internet 3 use (or other shared use on a network) from unauthorized surveillance or intervention by a PC 1 owner/user who is providing the shared resources.  To maintain the privacy necessary to operate such a cooperatively shared network arrangement, unauthorized surveillance or intervention must be carefully prevented by hardware/software /firmware or other means.

 Figure 17C therefore shows master M personal computer PC 1 (or PC microprocessor 90) using the slave S₂ microprocessor 40 of a different personal computer, PC 1', which is available for Internet 3 (or other net) shared use, while internal firewall 50' blocks unauthorized access into PC 1' by PC 1 (although PC 1' owner/user can always interrupt a shared operation and take back control and use of slave S' microprocessor 40, which then triggers off-loading action to compensate, as discussed above in Figures 16I-16J).

 Figure 17D shows a figure similar to Figure 17C, but showing a PC microprocessor 90 with a slave microprocessor 94 being used by Internet 3 users (or other net), so that at least one firewall 50 serves both to deny access such as surveillance by master M microprocessor 93 to an Internet 3 parallel processing (or multi-tasking) operation on slave S microprocessor 94 and to deny access to master M microprocessor 93 by Internet 3 (or other net) users of slave S microprocessor 94. It is presently contemplated that at least one internal firewall 50 is implemented by non-configurable hardware at the microchip level to provide the best protection against tampering with the internal firewall 50 by a PC 1 user, who has easier access to software or macro hardware such as PC motherboards to alter.  Also, non-configureable hardware denying access from the network is the most immune to hacking from any outside source, including the Internet, and can therefore be used either for general protection or to protect an innermost kernel of the most confidential of personal files (such as passwords or financial data) and the most critical of operating system components, such as the system bios or access to file alternation.

 Any of the embodiments shown in Figures 17A and 17B can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

 The flexible network architecture shown earlier in Figure 16K and other Figure 16 series (and other figures) have many applications, including their use to design improvements and alternatives to the network itself. In addition, the flexible network can be used to simulate and design personal computers PC 1 and particularly PC microprocessor chips 90 (and other microchips), which may be static or configurable (in response to the requirements of a given operation, like the Figure 16K network architecture) or a mix.

 The Figure 16K network architecture has capabilities that substantially exceed simulating the fairly simple binary circuit structure of a typical PC microprocessor 90 or other microchip, since any personal computer PC 1 or PC microprocessor chip 90 in the Figure 16K network can simulate much more than a simple binary circuit on/off state or other simple microchip circuit.  Any PC 1 or 90 in a Figure 16K network can represent virtually any number of states or conditions simulating any kind of circuit, however complex it might be, the only limit being the processing time required for what can be a very large number - thousands or millions - of personal computers PC 1 or PC microprocessors 90 to process the simulation; that is to say, there are only practical constraints, not theoretical ones, although increasingly larger numbers of processors are expected to be phased in, as discussed before.

 One potential related application of prior described network inventions is to simulating the unique "qubit" component necessary to construct a quantum computer, as well as a virtual quantum computer itself.

 Figures 18A-18D show designs for a virtual quantum computer or computers. Figure 18A shows personal computer PC 1 (or microprocessor 90) with the addition of a software program 151 simulating a "qubit" for a quantum computer or computers and thereby becoming a virtual qubit (VQ) 150, a key component of a quantum computer 153.  Figure 18B shows a personal computer PC 1 (or microprocessor 90) with a digital signal processor (DSP) 89 connected to a hardware analog device 152 simulating a qubit, with the PC 1 monitoring the qubit through the DSP 89, thereby simulating a virtual qubit (VQ) 150 for a quantum computer 153; this arrangement allows the option of simultaneous use of the PC 1 through multi-tasking for both digital and quantum computing.

 Figure 18C is like Figure 16A, but incorporating a virtual qubit in PC 1, so that a virtual quantum computer 153 can have any network architecture like those shown in Figures 16A-16Z and 16AA, as well as other figures of this application.

 As shown in Figure 18D, for example, a virtual qubits (VC) 150 network can provide complete interconnectivity, like Figure 13.  Virtual qubits VC 150 like those described in Figures 18A & 18B can be added to or substituted for microprocessors 30 and 40 in prior Figures 16B-16Q and 16V-16AA of this application, as well as earlier figures. As shown in those prior applications, the number of virtual qubits 150 is limited only to whatever is practical at any given time; in terms of development that means as few as a single qubit 150 in one or more networked personal computers PC 1 to begin, but the number of qubits 150 can become potentially extremely large, as indicated in previous figures.  Figure 18D shows a mix of wired 99 and wireless 100 connections.

 Any of the embodiments shown in Figures 18A-18D can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

 Like personal computers located in the home or office, personal computers PC 1 in automobiles 170 (including other transportation vehicles or other conveyances) are in actual use only a very small percentage of the time, with the average dormant period of non-use totaling as much as 90 percent or more.  Personal computers PC 1 are now being added to some automobiles and will likely become standard equipment over the next decade or so.  In addition, automobiles already have a very large number of microcomputers onboard in the form of specialized microprocessors 35 which are likely to become general parallel processors in future designs, as discussed earlier in this application.

 Automobiles therefore form a potentially large and otherwise unused resource for massive parallel processing through the Internet 3 and other networks, as described in earlier figures.  However, when idle and thus generally available for network use, automobiles lack their usual power source, the engine, which of course is then off, since it is too large to efficiently provide electrical power to onboard computers except occasionally. As shown in Figure 19, the car engine can have a controller (hardware, software or firmware or combination in the PC 1 (or other microprocessor 35), for example, connected to an automobile computer network 178 to automatically start the automobile engine in order to recharge the car battery 171 when the battery is low (and well before the battery is too low to start the engine), but the engine additionally needs to be controlled as above not to expend all available fuel automatically.

 Alternately, the automobile 170 can be fitted with a very small auxiliary engine-power electrical power generator 177 to provide power to the automobile's computer network; the engine of the generator 177 can be fed by the main engine fuel tank and controlled as above.

 Two solutions, not mutually exclusive, to alleviate (but not solve) the lack of power problem noted above are, first, adding an additional car battery 171' for network use (at least primarily) or, second, using a single battery but adding a controller in the PC 1, for example, that prevents the existing battery 171 from being discharged to a level near or below that which is needed to start the automobile 170.

 In addition, as shown in Figure 19, one or more solar power generating cells or cell arrays 172 can be incorporated in an automobile's outer surface, with generally the most effective placement being on a portion of the upper horizontal surface, such as a portion of the roof, hood, or trunk. For charging the automobile battery 171 when sunlight is not available, such as at night or in a garage, a focused or focusable light source 173 can provide external power to the solar panel.

 Alternately, a connection device 174 such as a plug for an external electrical power source can be installed on or near the outer surface of the automobile.  In addition, or independently, a connection device 175 for an optical fiber (or other wired) external connection to the Internet 3 or other net; an intermediate high transmission speed can also exist between the automobile network and a fiber optic connection to the Internet 3.  Alternately, a wireless receiver 176 located near where the automobile is parked, such as in a garage, can provide connection from the automobile's personal computer or computers PC 1 directly to the Internet 3 or to a network in a home or business like that shown in Figure 10I.

 Any of the embodiments shown in Figure 19 can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

 Figure 20A is like Figure 16Y, but in addition shows a slave microprocessor 40 functioning as S₁, the function of master having been temporarily or permanently offloaded to it by M₁ microprocessor 30.  Also in addition, Figure 20A shows the processing level of slave microprocessors 40, S₃₁ through S₃₄, each with a separate output/input communication link to a digital signal processor (DSP) 89 or other transmission/ reception component; the transmission linkages are shown as 111, 112, 113, and 114, respectively.  The DSP 89 can be connected to a wired 99 means such as optical fiber to the Internet (or other net), although non-optical fiber wire can be used (and probably does not require a DSP 89).

 Figure 20B is like Figure 16S, but with the same new additions described above in Figure 20A. Like Figure 16S, Figure 20B shows a detailed view of personal computer PC microprocessor 90₁, which is a personal computer on a microchip, including two more levels of parallel processing within the microprocessor 90. In addition, the two new levels of PC microprocessor 90 shown in Figure 20B are a second processing level consisting of PC microprocessors 90₂₁ through 90₂₄ and a third processing level consisting of PC microprocessors 90₃₁ through 90₃₁₆ (a third level total of 16 microprocessors 90). Each of the three processing levels shown in the Figure 20B example is separated between levels by an intermediate direct connection to the Internet 3 (or other network) and by four output lines from the higher processing level. For example, microprocessors 90₂₁ through 90₂₄ are shown receiving respectively from the outputs 111 through 114 from four slave microprocessors 94, S₃₁ through S₃₄ of PC microprocessor 90₁.

 Note that PC microprocessor 90₁ is shown in detail including all slave microprocessors 94, while other PC microprocessors 90 at the second and third processing levels do not, for simplicity and conciseness of presentation.  Note also that an additional processing level can be present, but is not shown for the sake of simplicity: personal computers PC 1 like Figure 20A can be used interchangeably with PC microprocessors 90.

 Figure 20B shows that between each processing level the output links from every PC microprocessor 90 can be transmitted from slave microprocessors 94 directly to PC microprocessors 90 at the next processing level below, such as from PC microprocessor 90₂₁ down to PC microprocessors 90₃₁ through 90₃₄, via the Internet 3 or other net. Each of the transmission/ reception links from those slave processing microprocessors 94 (S₃₁ through S₃₄), shown as 111, 112, 113, and 114 for PC microprocessor 90₁, can be transmitted or received on a different channel (and can use multiplexing such as wave or dense wave division) on an optical fiber line (because of its huge capacity, one optical fiber line is expected to be sufficient generally, but additional lines can be used) that connects preferably directly to PC microprocessor chip 90₁, which can incorporate a digital signal processor 89 or other connection component (of which there can be one or more) for connecting to the wired connection like fiber optic line, as shown, or wireless connection.

 Any of the embodiments shown in Figures 20A and 20B can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

 Figures 21A and 21B are like Figures 20A and 20B, but show additionally that all microprocessors 30, 40, 93, and 94 of PC 1 or PC 90₁ can have a separate input/output communication link to a digital signal processor (DSP) or other transmission/ reception connection component.  The additional communications linkages are shown as 141, 142, 143, and 144, which connect to M₁, S₁, S₂₁, and S₂₂, respectively, and connect to the network, including the Internet 3, the WWW, and equivalents or successors.  Like all preceding and subsequent figures, Figures 21A and 21B are schematic architectural plans of the new and unique components of the parallel processing system invention disclosed in this application and can represent either physical connections or virtual relationships independent of hardware. Figure 21B shows an embodiment in which the additional linkages lead through the Internet 3 to microprocessors PC 90₂₅-90₂₈.

 It is preferred that the additional communications linkages 141, 142, 143, and 144, as well as the original linkages 111, 112, 113, and 114 of Figures 20A and 20B, have a bandwidth sufficiently broad to at least avoid constraining the processing speed of microprocessors 30, 40, 93, and 94 connected to the linkages.  More preferably, the ultra high bandwidth of optical connections like optical fiber or omniguides or optical wireless provide external connections between PC 1 and PC 90₁ microprocessors that are far greater that the internal electrical connections or buses of those microprocessors, for example, by a factor of 10, or 100, or 1000, which are already possible with optical fiber, or 1,000,000, which is possible with optical omniguides, which are not limited to a small band of wavelengths like optical fiber; and future increases will be substantial, since the well established rate of increase for optical bandwidth is much greater than that for microprocessor speed and electrical connections. Wireless optical antennas that are positioned on the exterior of houses, buildings, or mobile reception site, instead of inside of glass or other windows, should significantly increase the number of optical wavelengths that can be sent or received by each of the wireless optical antennas; that way, the entire connection is freespace optical wireless, which allows for greater dense wave multiplexing and thereby greater bandwidth.

 A major benefit of the embodiments shown in Figs. 21A-21B is that PC 1 and PC 90₁ can function like the Figure 9 embodiment to efficiently perform operations that are uncoupled, so that each microprocessor M₁, S₁-S₃₄ can operate independently without microprocessors M₁, S₁, and S₂₁-S₂₂ being idled, as they might be in Figures 20A and 20B.  Another benefit is that for tightly coupled parallel operations microprocessors M₁, S₁, and S₂₁-S₂₂ can have broad bandwidth connections with microprocessors 30, 40, 93, or 94 that are not located on PC 1 or PC 90₁.  Thus the embodiments shown in Figures 21A and 21B provide an architecture that allows PC 1 or PC 90₁ the flexibility to function in parallel operations either like Figures 20A-20B embodiments or like the Figure 9 embodiment, depending on the type of parallel operation being performed. Studies indicate that single chip multiprocessors like PC 90₁ can also perform uniprocessor operations with a speed like that of uniprocessor architectures like wide-issue superscaler or simultaneous multithreading.

 Like Figures 20A and 20B, the preferred embodiment of Figures 21A and 21B includes broad bandwidth connection to the Internet 3 by wired means such as optical connection by fiber optic cable or omniguide or optical wireless, although other wired or non-wired means can be used with benefit.

 Another advantage of the embodiments shown in Figures 22A and 22B when functioning in the Figure 9 form of loosely coupled or uncoupled parallel processing or multitasking is that if PC 1 or PC 90₁ are functioning as a web server and typically uses only one microprocessor to do so, it can quickly add mirror web sites using one or more additional microprocessors to meet increasing volume of visits or other use of the web sit.  This replication of web sites on additional microprocessors in response to increasing load can also be done using the Figure 16 form of tightly coupled parallel processing. PC 1 and PV 90₁ or any of their microprocessors 30, 40, 93, and 94 or other components can also serve as a switch or a router, including other associated hardware/software/firmware network components.

 Any of the embodiments shown in Figures 21A and 21B can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

 Binary tree configurations of microprocessors shown in Figures 16, 20, and 21 can be laid out in 2D using an H-tree configuration, as shown in Figure 23 and can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

 Figure 22A shows a microprocessor PC 90₁ like that of Figure 21B, except that Figure 22A shows the microprocessors 93 and 94 each connecting to an optical wired interconnection 99' such as thin mirrored hollow wire or omniguide or optical fiber (and other very broad bandwidth connections can be used); the interconnect can include a digital signal processor 89' employed with a microlaser 150 and other components to transmit and receive digital data for microprocessors 93 and 94 into the optical wired interconnects 99' such as an omniguide using, for example, a specific wavelength of light for each separate channel of each separate microprocessor 93 and 94 utilizing dense wave multiplexing.

 Figure 22B shows and enlargement of the digital signal processor 89' with microlaser 150 with other transmission and reception components.

 Figure 22A shows a simple bus network connection architecture between the interconnect 99' and the microprocessors 93 and 94.  However, since the interconnection 99' is optical and the bandwidth available is very broad, the optical connection 99' allows connections between microprocessors 93 and 94 in PC 90₁ shown that are functionally equivalent to those shown in Figure 21B, which includes a representation of physical connections. The interconnects between microprocessors 93 and 94 like Fig. 21B are shown within the omniguide 99' shown in Figure 22A. In fact, the potential bandwidth of the optical interconnect 99' is so great that complete interconnection between all microprocessors 93 and 94 with PC 90₁ is possible, even for a much greater number of microprocessors either in a larger PC 90₁, like Figure 16T for example, or in other PC 90s, such as PC 90₂₁-90₂₄ and 90₃₁-90₃₁₆ in Figures 20B and 21B connected to PC 90₁ through a network such as the Internet 3 or WWW; consequently, any conventional network structure can be implemented. Consequently, the embodiment shown in Figure 22A has the flexibility of those of Figures 21A and 21B to function in parallel operations like either Figures 20A-20B embodiments or like the Figure 9 embodiment, depending on the type of parallel operation to be performed, or the Figure 16 embodiments.

 It should be noted that the optical interconnect 99' shown in Figure 22A can beneficially have a shape other than a thin wire or tube, such as an omniguide with any form or shape located above and connection to microlasers at a suitable location such as on or near the upper surface of the microchip PC 90₁ located at least at each microprocessor 93 and 94 or connected thereto, to take one example of the many possible workable configurations; the optical interconnect 99' and microlasers 150 and associated transmission and reception components can be located elsewhere on the microchip PC 90₁ with benefit. An omniguide can take a waveform shape or rely exclusively on a mirrored (or semi-mirrored) surface or surfaces (or combination of both shape and mirrored surface) to guide lightwave signals such as propagated by a microlaser substantially directly and/or by reflection.  As shown in Figure 22A, random access memory (RAM) 66 can be located on microchip PC 90₁ and also be connected directly or indirectly to the optical interconnect 99' (or use non-optical connections not shown), so that the microprocessors 93 and 94 and RAM 66 can communicate with a very broad bandwidth connection, including with RAM 66 and microprocessors 93 and 94 located off microchip PC 90₁ on the network including the Internet 3 and WWW.  Any other component of the PC 90 microchip can be connected with the optical interconnect 99' and more than one such interconnect 99' can be used on the same PC 90 or other microchip.  Microlasers 150 can include, for example, 5- to 20-micron-high vertical cavity-surface-emitting lasers (VCSELs), which can beam down waveguides built into a microchip; alternatively, freespace optics can be employed; and lenses can be employed.  Radio-frequency (RF) signals can also be used for similar interconnects 99'.

 Figure 22C is a side cross section of the microchip PC 90₁ shown in Figure 22A taken at hatched line 22C (which is abbreviated).  Figure 22C shows the location of the omniguide above the surface of the microprocessors 93 and 94 and RAM 66 and connecting them while also containing two or more microlasers 150 (associated DSP and other components not shown) proximate to each to contain the optical signal generated by the microlasers 150 so the signal can be transmitted between microprocessors 93 and 94 and RAM 66 either directly or by being reflected off the mirrored (or semi-mirrored) surface of the omniguide 99', for example. Each of the microprocessors 93 and 94 (or 30 or 40) and RAM 66 (or any other memory component such as L1 cache or L2 cache, for example, or other microchip component) can have one or more microlasers 150 and each such microlaser 150 can distinguish itself from other microlasers on the microchip (or off it) that also generate wavelength signals by using, for example, a distinct wavelength of light for data transmission and/or utilizing wave or dense wave multiplexing.  Note that Figure 22A is a topview of the microchip PC 90₁, which is a PC system on a microchip, any of which disclosed in this application can be also more generally any microchip with multiple processors. The microlasers 150 (and associated transmission and reception components such as DSP) that are associated with RAM (or parts of it) or other memory components can either provide data in response to direct inquiries or fetches made by a microprocessor 93 or 94 or can broadcast a continual stream of current data (continually updated and repeated in continuous cycle, for example) which is used by the microprocessor as needed.

 Any of the embodiments shown in Figures 22A and 22B can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

 It is currently contemplated that commercial embodiments of the networks, computers, and other components of the MetaInternet described in this application in the preceding Figures 1-22, including hardware, software, firmware, and associated infrastructure will be developed in conjunction and with the assistance of the Internet Society (ISOC), the World Wide Web Consortium (W3C), the Next Generation Internet (NGI), professional organizations like the Institute of Electrical and Electronics Engineers (IEEE) and the American National Standards Institute (ANSI) as well as other national and international organizations, and industry consortia drawn from the telecommunication, T.V. cable, ISP, network, computer, and software industries, as well as university and other research organizations, both U.S. and international, to set agreed upon operating standards which, although often arbitrary, are critical to efficient, reliable functioning of the MetaInternet.

 It is also presently contemplated that the Linux programming language will take a central role in the MetaInternet, since a homogeneous system has an advantage as most efficient and effective, and Linux is among the most stable, efficient higher level software available, one that has already established a preemininent role in distributed parallel processing. A heterogeneous MetaInternet is certainly feasible too, but less advantageous, as is the Java programming language, which excels in heterogeneous environments.  Although Linux is generally preferred over Java in keeping with the more effective homogeneous approach for parallel processing systems that can scale even to the massive numbers of PCs available on the Internet and WWW, either Java or principles employed in Java may be used with benefit, especially in certain cases like security, such as the use of "sandboxes" to provide secure execution environments for downloaded code (see page 39 of The Grid, Foster and Kesselman and associated bibliography references 238, 559, 555, and 370), although use of one or more internal firewalls as discussed earlier in Figure 10 and 17 to protect personal user files and critical hardware and software systems, such as the operating system may provide similar capability.

 It is also contemplated currently that, like the Linux programming language, the MetaInternet described in this application can be developed into a commercial form using open source principles for Internet-like standards for software and hardware connections and other components. Such open source development is anticipated to be exceptionally successful, like Linux, because much of it can be freeware, although modified with one vital enhancement to provide equity for significant contributors: minimal licensing fees that to be paid only by medium to large commercial and governmental entities at progressive rates based on financial size; the resulting funding can be used for significant financial and other awards for special research and development efforts relating to the MetaInternet and its open source development, particularly outstanding achievements by individuals and teams, especially independent developers and virtual teams, the awards also being progressive in terms of importance of contribution and most being peer-selected. Open source commercial development of the MetaInternet should therefore, like Linux, attract the most interested and best qualified technical expertise on the planet, all linked by the Internet and WWW to collaborate virtually in realtime 24 hours a day and 7 days a week, creating a virtual entity extraordinarily skilled in the existing art.

 It is also anticipated that the exclusive rights to the MetaInternet granted by patents issued on this application, particularly for the homogeneous embodiment of the MetaInternet - which is by far the most effective and efficient form - will ensure that the MetaInternet is homogeneous on critical hardware and software standards and protocols. That is because any heterogeneous systems cannot not compete commercially due to inherent inferiority in efficiency, while any competing homogeneous system would infringe the patents issuing from this and other applications and therefore be enjoined from operations.  The open MetaInternet standards would thus be patent-protected.

 As noted earlier, the Internet 3 and WWW (and successors or equivalents) are expected to ensure that any single design standard in widespread use, such as the Wintel standard (software/hardware) and the Apple MacIntosh standard (also both), are homogeneous as to MetaInternet parallel processing systems as outlined in this application, since the Internet and WWW and equivalents or successors make available such a large pool of homogeneous computers with the same standard, in ever increasingly close proximity as more and more PCs and other devices go online. The increasingly universal connection attribute of the Internet 3 and WWW and successors therefore create virtual homogeneity for most significant brands.

 The term homogeneous as it is used here refers to functional design standards primarily, not physical structure, for example, when applied to hardware.  In this sense, then, for example, the Intel Pentium II, the Advanced Micro Devices (AMD) K6-6, and the Cyrix MII microprocessor chips are functionally compatible and homogeneous with no need for special emulation software, although they are each structurally quite different and use different microcode at the microchip level. The new Transmeta microprocessors are expected to be functionally compatible and homogeneous through elaborate and highly efficient emulation, potentially an ideal microprocessor for the MetaInternet. In contrast, for example, the Apple G3 processor is also structural different but in addition requires a different operating system and is therefore not functionally compatible and not homogeneous with the Pentium II, K6-6, and MII microprocessors discussed above. Similarly, the MS DOS and DR DOS are functionally compatible software PC operating systems and homogeneous, even though their codes are different, whereas Apple MacIntosh operating systems are not functionally compatible or homogeneous with the two DOS systems, except with the addition of special emulation software, which is not efficient.  Substantially interchangeable use therefore is a defining element of homogeneity as used in this application. An example of a heterogeneous parallel processing system distributed among many computers which can be of any sort is the University of Virginia's Legion system, in contrast to the preferred homogeneous systems discussed above.

 This application encompasses all new apparatus and methods required to operate the above described network computer system or systems, including any associated computer or network hardware, software, or firmware (or other component), both apparatus and methods.  Specifically included, but not limited to, are (in their present or future forms, equivalents, or successors): all enabling PC and network software, hardware, and firmware operating systems, user interfaces and application programs; all enabling PC and network hardware design and system architecture, including all PC and other computers, network computers such as servers, microprocessors, nodes, gateways, bridges, routers, switches, and all other components; all enabling financial and legal transactions, arrangements and entities for network providers, PC users, and/or others, including purchase and sale of any items or services on the network or any other interactions or transactions between any such buyers and sellers; and all services by third parties, including to select, procure, set up, implement, integrate, operate and perform maintenance, for any or all parts of the foregoing for PC users, network providers, and/or others.

 The combinations of the many elements the applicant's invention introduced in the preceding figures are shown because those embodiments are considered to be at least among the most useful possible, but many other useful combination embodiments exist but are not shown simply because of the impossibility of showing them all while maintaining a reasonable brevity in an unavoidably long description caused by the inherently highly interconnected nature of the inventions shown herein, which generally can operate all as part of one system or independently.

 Therefore, any combination that is not explicitly described above is definitely implicit in the overall invention of this application and, consequently, any part of any of the preceding Figures and/or associated textual description can be combined with any part of any one or more other of the Figures and/or associated textual description of this application to create new and useful improvements over the existing art.

 In addition, any unique new part of any of the preceding Figures and/or associated textual description can be considered by itself alone as an individual improvement over the existing art.

 The forgoing embodiments meet the overall objectives of this invention as summarized above.  However, it will be clearly understood by those skilled in the art that the foregoing description has been made in terms only of the most preferred specific embodiments.  Therefore, many other changes and modifications clearly and easily can be made that are also useful improvements and definitely outside the existing art without departing from the scope of the present invention, indeed which remain within its very broad overall scope, and which invention is to be defined over the existing art by the appended claims.

[GloNetComp] [Who We Are] [PCT Applications] [US Patents] [In Depth]

Tuesday, May 15, 2001