Brief Description of the Drawings

 Figure 1 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a meter means which measures flow of computing during a shared operation such as parallel processing between a typical PC user and a network provider.

 Figure 2 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of another meter means which measures the flow of network resources, including shared processing, being provided to a typical PC user and a network provider.

 Figure 3 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of another meter means which, prior to execution, estimates the level of network resources, and their cost, of a shared processing operation requested by a typical PC user from a network provider.

 Figure 4A-4C are simplified diagrams of a section of a computer network, such as the Internet, showing in a sequence of steps an embodiment of a selection means whereby a shared processing request by a PC is matched with a standard preset number of other PC's to execute shared operation.

 Figure 5 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a control means whereby the PC, when idled by its user, is made available to the network for shared processing operations.

 Figure 6 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a signal means whereby the PC, when idled by its user, signals its availability to the network for shared processing operations.

 Figure 7 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a receiver and/or interrogator means whereby the network receives and/or queries the availability for shared processing status of a PC within the network.

 Figure 8 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a selection and/or utilization means whereby the network locates available PC's in the network that are located closest to each other for shared processing.

 Figure 9 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a system architecture for conducting a request imitated by a PC for a search using parallel processing means that utilizes a number of networked PC's.

 Figures 10A-10I are simplified diagrams of a section of a computer network, such as the Internet, showing an embodiment of a system architecture utilizing an internal firewall to separate that part of a networked PC (including a system reduced in size to a microchip) that is accessible to the network for shared processing from a part that is kept accessible only to the PC user; also showing the alternating role that preferably each PC in the network plays as either a master or slave in a shared processing operation involving one or more slave PC's in the network; and showing a home or business network system, which can be configured as an Intranet; in addition, showing PC and PC microchips controlled by a controller (including remote) with limited or no processing capability; and showing PC and PC microchips in which a internal firewall 50 is can be reconfigured by a PC user.

 Figure 11 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a system architecture for connecting clusters of PC's to each other by wireless means, to create the closest possible (and therefore fastest) connections.

 Figure 12 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a system architecture for connecting PC's to a satellite by wireless means.

 Figure 13 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a system architecture providing a cluster of networked PC's with complete interconnectivity by wireless means.

 Figure 14A is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a transponder means whereby a PC can identify one or more of the closest available PC's in a network cluster to designate for shared processing by wireless means. Figure 14B shows clusters connected wirelessly; Figure 14C shows a wireless cluster with transponders and with a network wired connection to Internet; Figure 14D shows a network client/server wired system with transponders.

 Figure 15 is a simplified diagram of a section of a computer network, such as the Internet, showing an embodiment of a routing means whereby a PC request for shared processing is routed within a network using preferably broad bandwidth connection means to another area in a network with one or more idle PC's available.

 Figures 16A-16Z and 16AB show a new hierarchical network architecture for personal computers and/or microprocessors based on subdivision of parallel processing or multi-tasking operations through a number of levels down to a processing level.

 Figures 17A-17D show a internal firewall 50 with a dual function, including that of protecting Internet users (and/or other network users sharing use) of one or more slave personal computers PC 1 or microprocessors 40 from unauthorized surveillance or intervention by an owner/operator of those slave processors.

 Figures 18A-18D show designs for one or more virtual quantum computers integrated into one or more digital computers.

 Figure 19 shows special adaptations to allow the use of idle automobile computers to be powered and connected to the Internet (or other net) for parallel or multi-tasking processing.

 Figures 20A and 20B show separate broad bandwidth outputs or inputs such as an optical connection like glass fiber from each microprocessor 40 or 94.

 Figures 21A and 21B are similar to Figures 20A and 20B, but show additionally that all microprocessors of a personal computer or personal computer on a microchip can have a separate input/output communication link to a digital signal processor (DSP) or other transmission/reception connection component.

 Figure 22A shows a PC microprocessor on a microchip similar to that of Figure 21B, except that Figure 22A shows microprocessors 93 and 94 each connecting to an optical wired connection 99' such as thin mirrored hollow wire or optical omniguide or optical fiber.

 Figure 23 shows a H-tree configuration of binary tree networks.

[GloNetComp] [Who We Are] [PCT Applications] [US Patents] [In Depth]

Friday, February 16, 2001